1. Field of the Invention
The present invention is related to level-shifting switches used in programmable memories and specifically to high voltage CMOS level-shifting switches for those memories.
2. Art Background
In the field of memory devices such as EPROMs and EEPROMs, it is common to use a high voltage switch to achieve level shifting between voltage levels to activate the memories. A typical high voltage switch using the complementary metal oxide (CMOS) process is illustrated in FIG. 1. As shown in FIG. 1, the voltage Vpp represents the programming voltage for the PROM, which is typically 12 volts or higher. Input voltage Vin is applied to an n-channel MOSFET driver MN1 at its gate, while an inverted Vin is applied to the gate of another n-channel MOSFET driver MN2. Two p-channel MOSFET loads MP1 and MP2 are coupled between the n-channel MOSFET drivers MN1 and MN2 and the voltage Vpp. The gate of the p-channel MOSFET MP1 is connected to the drain nodes of transistors MP2 and MN2, which also forms the output voltage Vout. Similarly, the gate of the p-channel MOSFET MP2 is connected to the drain nodes of transistors MP1 and MN1, which becomes the complementary output voltage Vout-NOT.
Referring to FIG. 1, the operation of a typical CMOS switch is described as follows. When the input voltage Vin is low in the digital sense, the n-channel transistor MN1 is non-conducting. If the p-channel transistor MP1 is ON, the voltage level at Vout-NOT will tend to be pulled to Vpp, which continues to bias the p-channel transistor MP2 into an OFF state. As such, the voltage level at Vout will be pulled to low due to Vin-NOT at the gate of the n-channel transistor MN2. It would be apparent to those skilled in the art that the p-channel transistors should be sized to be weaker than the n-channel transistors to generate proper transitions. Typically, the n-channel transistors are fabricated to be at least twice as wide as the p-channel transistors.
A common problem known as gate-aided breakdown occurs at the junction edge of the CMOS switch shown in FIG. 1. The breakdown occurs in the p-channel transistors when the gate is biased towards a high potential of Vpp with the diffusion at either the drain or source being biased low. Similarly, the breakdown occurs in the n-channel transistors when the gate is biased towards a high negative potential with the diffusion being pulled positive high. The problem of gate-aided breakdown is typically prevented by having a cascode guard device in series with the switching devices as shown in the improved switch in FIG. 2.
Reference is now made to FIG. 2, where an n-well CMOS high voltage level-shifting switch is shown. As shown in FIG. 2, the p-channel guard devices 220 and 260 are connected in series with the p-channel switching devices 210 and 250, respectively. The n-channel guard devices 230 and 270 are connected in series with the n-channel switching devices 240 and 280, respectively. Input voltage at Vin 241 is typically 3 volts to 6 volts. A voltage Vmp 221 is applied to the gates of guard devices 220 and 260 as the gate bias for the guard devices. A voltage Vmn 231 is also applied to the gates of guard devices 230 and 270 as the gate bias voltage. Note that the p-channel devices 210 and 220, 250 and 260 have their wells coupled to Vpp 200, respectively. A cross-sectional view of the p-channel devices 250 and 260 from one side of the switch is shown in FIG. 3 to help illustrate another problem still associated with the conventional CMOS switch.
Referring to FIG. 3, when the gate 353 of device 350 is pulled to Vpp during switching, the p-channel device 350 is effectively shut off. Here, gate-aided breakdown is already prevented by the voltage applied to the gate 363 of device 360. However, the drain 361 of device 360 is switched and pulled towards 0 volts, thus causing a reverse junction breakdown between p+ drain 361 and n-well 362 because n-well 362 is coupled to a high Vpp potential. For sub-micron devices, this reverse bias potential of (Vpp-Vss), or Vpp when Vss=0 volts, creates a serious problem for the devices.
As will be described in the following, the present invention provides an improved high voltage CMOS switch with guarding against reverse junction breakdown, as well as gate-aided breakdown.